1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which is readily capable of eliminating crosstalk noise which is generated on the reception side when sending clock signals in the same direction by using a plurality of wirings that are connecting the circuits.
2. Description of the Prior Art
The advancement of the processing speed of the computer or the like in recent years is remarkable, as exemplified by the operating speed of several hundreds MHz for the microprocessor of the personal computer, and a high rate data transfer in the band of several GHz is being obliged in the network market. Accompanying such a trend, the electrical signals that flow in the wirings (signal lines) that connect circuits within the IC become also high rate, making the effect of crosstalk between adjacent signals increasingly conspicuous.
Since the crosstalk gets the larger the smaller the distance between the wirings, it is a factor of obstruction standing in the way toward miniaturization and high density of the high speed circuit. In particular, when the width of data handled becomes large such as 32 bits or 64 bits, propagation of many signals in the same direction occurs more frequently, and the possibility of causing malfunctions of the system is increased due to superposition of noises of a plurality of noise sources.
FIG. 19 is a circuit diagram showing the internal configuration of a conventional semiconductor integrated circuit. FIG. 19 shows a circuit in which a plurality of clock signals CK1 to CK8 having identical delay difference between the signals, output from a delay locked loop (referred to as DLL hereinafter) circuit 101, are supplied to a data comparator (referred to as DCMP hereinafter) via an insert part 1402.
The DLL circuit 101 generates n (n is an integer of 2 or more, and it is 8 in this example) clock signals Cki (i is an integer of 1 to n) each of them being delayed by a delay time of ixc3x97T (T is a constant time) from a reference signal RCLK. In the buffer insert part 1402, there are provided buffers B1 to B8 corresponding to the clock signals CK1 to CK8. The buffers B1 to B8 are provided to prevent the attenuation of respective clock signals CK1 to Ck8 by the parasitic capacitances and the parasitic resistances of the wirings that connect the DLL circuit 101 to the DCMP circuit 103.
The clock signals CK1 to CK8 output from the DLL circuit 101 are input respectively to the input terminals of the buffers B1 to B8 via input wirings NI1 to NI8. The clock signals CK1 to CK8 output from the output terminals of the buffers B1 to B8 are input respectively to the corresponding input terminals of the DCMP circuit 103 via output wirings NO1 to NO8.
In FIG. 19, CI1, CI2, CI3, CI4, CI5, CI6 and CI7 represent the parasitic capacitances present between the input wirings NI1 and NI2, between NI2 and NI3, between NI3 and NI4, between NI4 and NI5, between NI5 and NI6, between NI6 and NI7 and between NI7 and NI8, respectively. Similarly, CO1, CO2, CO3, CO4, CO5, CO6 and CO7 represent the parasitic capacitances present between output wirings NO1 and NO2, between NO2 and NO3, between NO3 and NO4, between NO4 and NO5, between NO5 and NO6, between NO6 and NO7 and between NO7 and NO8, respectively.
FIG. 20 is a waveform diagram showing the clock signals CK1 and CK2, and the signals on the input wirings NI1 and NI2 connected to the input terminals of the buffers B1 and B2. The NI1 in FIG. 20 shows the clock signal flowing on the input wiring NI1, and the NI2 in FIG. 20 shows the clock signal CK2 flowing on the input wiring NI2.
The rise edge tr of the clock signal CK1 is propagated to the input terminal of the buffer B1 through the input wiring NI1. Owing to the parasitic capacitance CI1 and a wiring resistance, not shown, the tr edge of the clock signal CK1 arrives at the input terminal of the buffer B1 after a delay time of xcfx841. Moreover, the rise edge tr of the clock signal CK2 is propagated to the input terminal of the buffer B2 through the input wiring NI2. Owing to the parasitic capacitances CI1 and C2 and wiring resistances, not shown, the tr edge of the clock signal CK2 arrives at the input terminal of the buffer B2 with a delay time of xcfx842 after leaving the DLL circuit 101.
At this time, due to the fact that the input wiring NI1 of the buffer B1 and the input wiring NI2 of the buffer B2 are disposed adjacent in parallel, crosstalk noise caused by the tr edge of the clock signal CK1 mingles with the clock signal CK2 on the input wiring NI2 via the parasitic capacitance CI1.
As can be seen from FIG. 20, the edge tr of the clock signal CK2 flowing on the input wiring NI2 is located, as seen on the time base, in the vicinity of the edge tr of the clock signal CK1 flowing on the input wiring NI1.
Accordingly, low level of the clock signal CK2 flowing on the input wiring NI2 fluctuates as shown in FIG. 20 due to the effect of the crosstaslk, and a deviation corresponding to a minute time xcex94tr is generated in the tr edge of the clock signal CK2 on the input wiring NI2. In this manner, the crosstalk noise affects the tr edge of the clock signal CK2 flowing on the input wiring NI2.
Analogously, the crosstalk noise caused by the tr edge of the clock signal CK2 mingles with the clock signal CK1 flowing on the input wiring NI1 via the parasitic capacitance CI1. The crosstalk noise affects the tr edge of the clock signal CK1 flowing on the input wiring NI1, and generates a deviation of a minute time in the tr edge of the clock signal CK1.
Although the tr edge of rise alone has been mentioned in the above, similar situation occurs of course concerning the tf edge of the fall. For example, crosstalk noise caused by the tf edge of the clock signal CK1 mingles with the clock signal CK2 on the input wiring NI2 via the parasitic capacitance CI1. The crosstalk noise affects the tf edge of the clock signal CK2 flowing on the input wiring NI2, and generates a deviation corresponding to a minute time xcex94tf in the clock signal CK2.
As in the above, although no time difference exists between the tr edge and the tf edge of each of the adjacent clock signals CK1 to CK8 in the semiconductor integrated circuit in FIG. 19, deviations of minute time xcex94tr and xcex94tf are generated respectively in the tr edge and the tf edge of respective clock signals CK1 to CK8, owing to the effect of crosstalk noise generated by the interference between respective adjacent clock signals CK1 to CK8. This fact gives rise to a problem of increase in the skew (phase deviation) among the clock signals CK1 to CK8, and jitter (phase fluctuation) in each of the clock signals CK1 to CK8.
Generally, crosstalk noise attenuates in inverse proportion to the distance between the clock signals. Consequently, the solution to the problem will be obtained by simply taking the spacing between the signal lines large enough. However, taking the spacing between the signal lines large leads to an increase in the wiring area, and results in a large area of the IC which makes it fail to be a practical solution.
Next, by making correspondence to the circuit diagram in FIG. 19, a design method for determining the circuit layout and wiring of the semiconductor integrated circuit will be described in detail. FIG. 21 is a diagram showing a series of flows as will be described in the following. It starts with determination step 1602 of the layout positions of the DLL circuit 101 and the DCMP circuit 103, and after determination of the layout and wiring of the buffer insert part 1402, confirms the skews between the clock signals CK1 to CK8 and the jitters of the clock signals CK1 to CK8 in the buffer insert part 1402. After connecting among the DLL circuit 101 and the buffer insert part 1402 and the DCMP circuit 103, skews between the clock signals CK1 to CK8 output from the DLL circuit 101 and the jitters of the signals CK1 to CK8 are confirmed, the skews between the clock signals CK1 to CK8 and the jitters of the clock signals CK1 to CK8 input to the buffers B1 to B8 are confirmed, and the skews between the clock signals Ck1 to CK8 and the jitters of the clock signals CK1 to CK8 input to the DCMP circuit 103 are confirmed, to carry out a characteristic confirmation step 1610 for confirming whether or not the skews and the jitters in each of these steps satisfy the standards.
First, the engineer in charge of the design determines the layout positions of the DLL circuit 101 and the DCMP circuit 103 from the sizes and the order of the signal lines of the DLL circuit 101 and the DCMP circuit 103 (step 1602 in FIG. 21). Next, the designer makes rough estimate of parasitic capacitance per unit area of the wirings based on the layout positions of the DLL circuit 101 and the DCMP circuit 103 determined by step 1602, and determines required stage number of each of the buffers B1 to B8 of the buffer insert part 1402 by finding the drive capability per unit stage of the buffer insert part 1402 (step 1603).
Following that, the designer determines the size of the buffer insert part 1402 from the required stage number derived in step 1603 (step 1604), and carries out layout and wiring of each of the buffers B1 to B8 in the buffer insert part 1402 based on the determined size of the buffer insertion part 1402 (step 1605).
After completion of the wirings of the buffer insert part 1402, the designer executes a circuit simulation of the buffer insert part 1402 based on the layout of the buffer insert part 1402 and extracted circuit data on the parasitic capacitances and the parasitic resistances from the wiring result (step 1606). Then, the designer carries out characteristic confirmation whether or not the skews between the clock signals CK1 to CK8 and the jitters of the clock signals CK1 to CK8 satisfy the standards in the buffer insert part 1402 from the result of the circuit simulation in step 1606 (step 1607). When the result of the circuit simulation in step 1606 satisfies the standards, the designer wires between the DLL circuit 101 and the buffer insert part 1402, and between the buffer insert part 1402 and the DCMP circuit 103 as shown in FIG. 19 (step 1608). After completion of the wirings, the designer executes simulation of the entire circuit in FIG. 19 based on circuit data on the parasitic capacitances and the parasitic resistances extracted from the result of wirings of the buffer insert part 1402 and the DLL circuit 101 and the DCMP circuit 103 (step 1609).
The designer then carries out characteristic confirmation which checks whether or not the skews between the clock signals CK1 to CK8 and the jitters of the signals CK1 to CK8 satisfy the standards for the entire circuit in FIG. 19 from the result of the circuit simulation in step 1609 (step 1610). When the result of the circuit simulation in step 1610 satisfies the standards, the designer prepares art work data (referred to as GDS data hereinafter) (step 1611), and completes the design.
When the skews between the clock signals CK1 to CK8 and the jitters of the clock signals CK1 to CK8 do not satisfy the standards in step 1610, the designer decides whether or not it is possible to satisfy the standards by the wiring change between the DLL circuit 101 and the buffer insert part 1402, and the buffer insert part 1402 and the DCMP circuit 103 (steps 1613 and 1614). If it is decided to be possible, the designer changes the wirings between the DLL circuit 101 and the buffer insert part 1402, and the wirings between the buffer insert part 1402 and the DCMP circuit 103 (step 1615), and returns to step 1609.
When it is decided that the standards cannot be satisfied by the wiring changes in step 1614, or the skews between various clock signals CK1 to CK8 and the jitters of respective clock signals CK1 to CK8 are not satisfied in step 1607, the designer decides whether or not it is possible to satisfy the standards by changing the layout and the wirings of the buffer insert part 1402 (steps 1616 and 1617). When decided that it is possible, the designer changes the layout and the wirings of the buffer insert part 1402 (step 1618), and returns to step 1606.
When decided that it is not possible to satisfy the standards by the change in the layout and the wirings, the designer decides whether it is possible to satisfy the standards by a size change in the buffer insert part 1402 (steps 1619 and 1620). When decided that it is possible, the designer changes the size of the buffer insert part 1402 (step 1621), and returns to step 1605.
When decided that it is not possible to satisfy the standards by a size change in step 1620, the designer decides whether or not it is possible to satisfy the standards by a stage number change in the buffer insert part 1402 (steps 1622 and 1623). When decided that it is possible, the designer changes the stage number of the buffer insert part 1402 (step 1624), and returns to step 1604. When decided that it is not possible to satisfy the standards by a stage number change in step 1623, the designer changes the layout positions of the DLL circuit 101 and the DCMP circuit 103 (step 1625), and returns to step 1603.
As in the above, in the conventional design of a semiconductor integrated circuit, when the skews between the clock signals CK1 to CK8 and the jitters of the clock signals CK1 to CK8 do not satisfy the standards in the characteristic confirmation step 1607 of the buffer insert part 1402 or the characteristic confirmation step 1610 of the overall circuit, it has been necessary to carry out a wiring change between the DLL circuit 101 and the buffer insert part 1402, and between the buffer insert part 1402 and the DCMP circuit 103 (step 1615), the layout change and the wiring change of the buffer insert part 1402 (step 1618), the size change of the buffer insert part 1402 (step 1621), the stage number change in the buffer insert part 1402 (step 1624), and the layout position change of the DLL circuit 101 and the DCMP circuit 103 (step 1625).
As described in the above, in the conventional semiconductor integrated circuit, there is a problem that the skews between the clock signals CK1 to CK8 and the jitters of respective clock signals CK1 to CK8 are increased due to the crosstalk noise among a plurality of clock signals CK1 to CK8. Generally speaking, the effect of crosstalk noise can be reduced by giving shield wirings between the wirings of respective clock signals CK1 to CK8, or by increasing the separation between the clock signals CK1 to CK8. However, in the former technique it becomes necessary to give additional wiring and spacing between the clock signal wirings as a result of insertion of the shield, and in the latter technique the space between the clock signal wirings is similarly increased, so that it leads to a drawback in that the area of the IC is enlarged.
In a structure in which shield wirings are provided between clock signals CK1 to CK8, it is necessary to have the spacing between the signal wirings somewhat larger than the spacing of design reference for the semiconductor integrated circuit. For this reason, in the example shown in FIG. 19, for example, when shield wirings are provided between the clock signals CK1 to Ck8, the area of wirings becomes about 2.5 times as large as that of the case without the shield wirings. As a result, the wiring capacitance per unit length for each of the clock signals CK1 to CK8 is also increased, the stage number of insertion of the buffers B1 to B8 for avoiding attenuation due to parasitic capacitances and parasitic resistances is increased, the overall area of the semiconductor integrated circuit becomes close to three times as large, and a vicious cycle is generated in which the effect of manufacturing variation between the buffers B1 to B8 generated in the processes of manufacture is added to the skews between the clock signals CK1 to CK8 and the jitters in respective clock signals CK1 to CK8. Because of this, it leads to a problem in that the standards are not satisfied in high speed design and the yield is reduced. Meanwhile, in a structure in which the spacing between the clock signal wirings are expanded, the spacing between the wirings that relaxes the effect of crosstalk noise generally requires more than several [xcexcm], and results in the total area of the semiconductor integrated circuit reaching to more than five times as large according to the design reference in the sub-micron era, which is impractical.
Furthermore, in the conventional semiconductor integrated circuits, it is necessary in design to go back to a preceding step for redesigning, which gives rise to a problem of long design time because of a large number of return steps.
Object of the Invention
It is the object of the present invention to provide a semiconductor integrated circuit which can reduce the skews between the clock signals and the jitters of respective clock signals without increasing the area of the semiconductor integrated circuit.
Summary of the Invention
In a semiconductor integrated circuit having a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each of which is delayed by a delay time of ixc3x97T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using the n clock signals input from the first circuit via n signal wirings, when edge positions of two clock signals transmitted on two adjacent signal wirings, as seen on the time base, are separated in time by a time larger than T, at least for a part of the n signal wirings.